The present invention relates to an output circuit disposed within a semiconductor integrated circuit device, for outputting signals from other circuits within the integrated circuit device.
An example of conventional output circuits for a semiconductor integrated circuit device is shown in FIG. 1. The output circuit 1 comprises an output section 101 and a control section 102. The output section 101 includes a P-type MOSFET 5 and an N-type MOSFET 6 whose conduction paths are connected in series between a voltage supply +V.sub.cc and a point of ground potential. The junction of the conduction paths of the MOSFET's 5 and 6 provides an output node N1. The control section 102 comprises a NAND circuit 3 which has its output coupled to the gate of P-type MOSFET 5, and a NOR circuit 4 which has its output coupled to the gate of N-type MOSFET 6. An output control signal OE and an input signal O are supplied to NAND circuit 3, and an inverted version of the output control signal OE from an inverter 2 and the input signal O are supplied to NOR circuit 4. Output control signal OE and the input signal O are produced by other circuits within the semiconductor circuit device in which the output circuit 1 is disposed.
When output control signal OE is at a low (L) level, output node N1 exhibits a high impedance state, and when the output control signal OE is at a high (H) level, an output signal DO is developed at the same level as the input signal O, at the output node N1.
More specifically, when the output control signal OE is at the L level, the output signal from NAND circuit 3 is at the H level and, therefore, P-type MOSFET 5 is non-conductive, regardless of whether input signal O is at the H level or at the L level. At the same time, since an H level signal resulting from inverting the L level output control signal OE in the inverter 2 is applied to NOR circuit 4, the output signal from NOR circuit 4 is at the L level and, therefore, N-type MOSFET 6 is also non-conductive, regardless of whether the input signal O is at the H level or at the L level. Accordingly, a high impedance state is exhibited at output node N1.
Next, let it be assumed that the output control signal OE is at the H level and the input signal O is also at the H level. The output signal from the NAND circuit 3, to which both the output control signal OE and the input signal O are applied, is at the L level and, therefore, P-type MOSFET 5 is turned on. NOR circuit 4 receives the inverted version of the H level output control signal OE, which is at the L level, and the input signal O at the H level, and, accordingly, develops an output signal at the L level. Therefore, N-type MOSFET 6 is non-conductive. As a result, output node N1 is placed at the H level which is the same level as input signal O.
When the output control signal OE is at the H level and input signal O is at the L level, NAND circuit 3 develops an output signal at the H level and, therefore, P-type MOSFET 5 is non-conductive. NOR circuit 4 receives an L-level signal, which is the inverted version of the H level output control signal OE, and the L level input signal O. Accordingly, the output of NOR circuit 4 is at the H level so that N-type MOSFET 6 is conductive. Consequently, output node N1 is at the L level same as output signal O.
A circuit board 103 shown in FIG. 2 contains semiconductor integrated circuits 9 and 10 which may be a processor and a co-processor. Semiconductor integrated circuit 9 includes a logic circuit 7 and an output circuit 110, and semiconductor integrated circuit 10 includes a logic circuit 8 and an output circuit 120. The output circuit shown in FIG. 1 may serve as output circuits 110 and 120.
Logic circuit 7 includes a latch circuit 72 which couples a signal DO2 from output circuit 120 of semiconductor circuit 10 to a logic gate 71 when a H level clock signal C.sub.1 is applied to latch circuit 72 from a clock signal generating circuit (not shown). Latch circuit 72 latches signal DO2 from output circuit 120 at the falling edge of clock signal C.sub.1. Logic gate 71 performs an arithmetic operation on the signal applied thereto, and couples the result of the arithmetic operation to a latch circuit 73. Latch circuit 73 receives a clock signal c.sub.2 from the clock signal generating circuit (not shown), and couples the output form logic gate 71 to a logic gate 74 when clock signal C.sub.2 is at its H level. Latch circuit 73 latches the output from the logic gate 71 at the falling edge of the clock signal C.sub.2. The logic gate 74 performs an arithmetic operation on the signal from the latch circuit 73 and couples the operation result to the output circuit 110 as an input signal 01 in synchronization with the rising edge of clock signal C.sub. 2. The logic circuit 7 also includes an output control signal generating circuit 75. When logic gate 74 is ready for providing the arithmetic operation result, the output control signal generating circuit 75 provides a H-level output control signal OE1 to output circuit 110 in synchronization with a rising edge of the clock signal C.sub.2. After coupling the operation result from logic gate 71, output control signal generating circuit 75 restores output control signal OE1 to the L level in synchronization with the rising edge of clock signal C.sub.2. (See FIGS. 3b and 3d.) Thus, output circuit 110 produces an output signal DO1 at the same level as the output signal 01 of the logic gate 74.
Similar to the logic circuit 7, the logic circuit 8 also includes a latch circuit 81, a logic gate 82, a latch circuit 83, a logic gate 84, and an output control signal generating circuit 85, and operates in a similar manner to logic circuit 7. Respective component circuits of logic circuit 8 develop signals similar to those which are generated by the corresponding component circuits of logic circuit 7.
Latch circuit 72, of the logic circuit 7, is coupled to output circuit 120 via a line 121 on board 103, and latch circuit 81 of logic circuit 8 is coupled to output circuit 110 via a line 122 on board 103.
For the correct operation of the semiconductor integrated circuits 9 and 10, a time period T.sub.0 between the rising edge of the output control signal OE1, or the output control signal OE2 (from the output control signal generating circuit 85), and the occurrence of the output signal DO1, or the output signal DO2 (from output circuit 120), must be within a time period T.sub.1 extending between the rising edge of clock signal C.sub.2 and the falling edge of clock signal C.sub.1, which occurs after the rising edge of signal C.sub.2. In semiconductor integrated circuit 9, for example, the input signal 01, applied to the output circuit 110, is the result of the arithmetic operation performed by the logic gate 74 on the output of the latch circuit 73. Latch circuit 73 couples the result of the arithmetic operation performed by the logic gate 71 to the logic gate 74 in synchronization with the rising edge of clock signal C.sub.2. Input signal 01 appears as output signal DO1 through output circuit 110. Accordingly, when the output control signal OE1 occurs in synchronization with the rising edge of clock signal C.sub.2, there is a delay between the rising edge of the output control signal OE1 and the occurrence of the output signal DO1. The delay is provided by logic gate 74 and output circuit 110. If logic gate 74 provides a longer delay and, accordingly, input signal 01 and output signal DO1 are developed after clock signal C.sub.1 changes to the L level, as indicated by dash-and-dot lines in FIGS. 3c and 3e, the output signal DO1 from output circuit 110 is not latched properly.
Accordingly, it is necessary to choose and place on circuit board 103 semiconductor integrated circuits 9 and 10 that can produce output signals DO1 and DO2 within time period T.sub.1.
A reference time period is used for the selection of semiconductor integrated circuits suitable for use as circuits 9 and 10. This reference time period is such that if the output signals DO1 and DO2 are generated within the reference time period, those semiconductor integrated circuits which generate such output signals are judged to be acceptable, whereas those semiconductor integrated circuits which do not generate the output signals DO1 or DO2 within the reference time period are rejected. The reference time period is obtained by simulating circuits 9 and 10, and an arrangement and interconnections of semiconductor integrated circuits on circuit board 103.
It is difficult, however, to produce characteristic models of transistors in semiconductor integrated circuits 9, 10 and of signal transmission paths. Therefore, the precision of the simulated reference time period for selection is low. Accordingly, the reference time period used for selection of suitable semiconductor integrated circuits is formulated by adding a margin of error to the simulated or calculated reference time period. This produces such tight tolerances such that even acceptable semiconductor integrated circuits may be unnecessarily rejected.